Freescale Semiconductor /MK61F15WS /DDR /CR13

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR13

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TREFINT0RESERVED 0 (0)PD 0RESERVED

PD=0

Description

DDR Control Register 13

Fields

TREFINT

Reserved

RESERVED

Reserved

PD

Power Down

0 (0): Enable full power state

1 (1): The memory controller completes processing of the current burst for the current transaction (if any), issues a precharge all command, and disables the clock enable signal to the DRAM devices. Any subsequent commands in the command queue are suspended until this bit is cleared.

RESERVED

Reserved

Links

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